Publications

Book Chapters

1- Sidi Ahmed Mahmoudi,, Erencan Ozkan, Pierre Manneback, and Suleyman Tosun, Taking Advantage of Heterogeneous Platforms in Image and Video Processing, in the book High-Performance Computing on Complex Environments, John Wiley & Sons, ISBN: 978-1-118-71205-4, pp. 429-450, July 2014.

2- Ozcan Ozturk and Suleyman Tosun, Enabling Network Security in HPC Systems Using Heterogeneous CMPs, in the book High-Performance Computing on Complex Environments, John Wiley & Sons, ISBN: 978-1-118-71205-4, pp. 383-400, July 2014.

Journals (ISI Indexed)

1- Tosun, Suleyman, Vahid B. Ajabshir, Ozge Mercanoglu, and Ozcan Ozturk. "Fault-Tolerant Topology Generation Method for Application-Specific Network-on-Chips." Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 34, no. 9 (2015): 1495-1508.

2- Suleyman Tosun, Ozcan Ozturk, Erencan Ozkan, and Meltem Ozen, Application Mapping Algorithms for Mesh-based Network-on-Chip Architectures, Journal of Supercomputing, 71:995-1017, 2015.

3- Ozturk, Ozcan, Ismail Akturk, Ismail Kadayif, and Suleyman Tosun. "Energy reduction in 3D NoCs through communication optimization." Computing 97, no. 6 (2015): 593-609.

4- S. Tosun, Y. Ar, and S. Ozdemir, Application Specific Topology Generation Algorithms for NoC Design, Computers & Digital Techniques, IET , vol.6, no.5, pp.318-333, September 2012.

5- S. Tosun, Energy- and reliability-aware task scheduling onto heterogeneous MPSoC architectures, The Journal of Supercomputing, 62, 1, 265-289, 2012.

6- S. Tosun, Cluster-based application mapping method for Network-on-Chip, Advances in Engineering Software, Vol. 42, No. 10, pp. 868-874, 2011. 

7- S. Tosun, New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs Journal of Systems Architecture, Special Issue on On-Chip Parallel And Network-Based Systems, Vol. 57, No. 1, pp. 69-78, 2011. 

8- S. Tosun, FIT: Fast Irregular Topology generation algorithm for application specific NoCs, IEICE Electronics Express, Vol. 7, No. 15, pp.1132-1138, 2010.

9- K. Polat, S. Gunes, and S. Tosun, Diagnosis of heart disease using artificial immune recognition system and fuzzy weighted pre-processing, The Journal of the Pattern Recognition Society, Pattern Recognition, Vol.39, pp 2186-2193, 2006. 

Other Journal Publications

1- Y. Kim, S. Tosun, H. Koc, S. Kopuri, and N. Mansouri, Automating Formal Verification of Synthesized RTLs with Pipelined Iterative Constructs, International Journal of Modeling and Simulation (IJMS), Vol. 25, Issue 3, 2005. (EI-Compendex)

2- Y. Yavuz, B. Tugrul, and S. Tosun, Hilbert Curve Based Bucket Ordering for Global Illumination, Journal of Computing, Volume 2, Issue 9, September 2010.

3- Hakduran Koc, Suleyman Tosun, Mahmut Kandemir and Ehat Ercanli, Improving Memory Space Utilization in Multi-core Embedded Systems using Task Recomputation; International Journal of Computer Science and Network, Volume 1, Issue 5, pp. 27-34, October 2012.

Conference Papers

1- Sincan, Ozge Mercanoglu, Vahid Babaei Ajabshir, Hacer Yalim Keles, and Suleyman Tosun. "Moving object detection by a mounted moving camera." In EUROCON 2015-International Conference on Computer as a Tool (EUROCON), IEEE, pp. 1-6. IEEE, 2015.

2- Vahid Babaei Ajabshir and Suleyman Tosun, Fault-Tolerant Routing for Irregular-Topology-based Network-on-Chips, The Second International Symposium on Computing and Networking, CANDAR'14, Mt. Fuji, Shizuoka, Japan, December 10-12, 2014.

3- Tosun, Suleyman; Ajabshir, Vahid Babaei; Mercanoglu, Ozge; Ozturk, Ozcan, Fault-Tolerant Irregular Topology Design Method for Network-on-Chips, Digital System Design (DSD), 2014 17th Euromicro Conference on , vol., no., pp.631,634, 27-29 Aug. 2014.

4- Suleyman Tosun, Yilmaz Ar, and Suat Ozdemir, Power-Aware Topology Generation Algorithm for Application Specific NoC Design, in Proc. of AICT 2012, Georgia, Tbilisi, 17-19 October 2012.

5- M. Ozen and S. Tosun,  Genetic Algorithm based NoC Design with Voltage/Frequency Islands  5th International Conference on Application of Information and Communication Technologies, AICT2011, Azerbaijan, Baku, 2011.

6- S. Tosun, O. Ozturk, and M. Ozen, An ILP Formulation for Application Mapping onto Network-on-Chips, 3rd International Conference on Application of Information and Communication Technologies, AICT2009, Azerbaijan, Baku, 14-16 October 2009.

7- Y. Yavuz and S. Tosun, Parallelization of Render Engine for Global Illumination of Graphics Scenes, 3rd International Conference on Application of Information and Communication Technologies, AICT2009, Azerbaijan, Baku, 14-16 October 2009.

8- Y. Ar, S. Tosun, and H. Kaplan, TopGen: A New Algorithm for Automatic Topology Generation for Network on Chip Architectures to Reduce Power Consumption, 3rd International Conference on Application of Information and Communication Technologies, AICT2009, Azerbaijan, Baku, 14-16 October 2009.

9- Y. Yavuz ve S. Tosun, Parallelization of Photon Mapping Algorithm for Global Illumination, The National Symposium on Electrical-Electronics and Computer Engineering, ELECO 2008, Bursa, Turkey, 2008.

10- S. Tosun ve Y. Yavuz, Task Scheduling On Heterogeneous Chip Multiprocessors for Reducing Energy, The National Symposium on Electrical-Electronics and Computer Engineering, ELECO 2008, Bursa, Turkey, 2008.

11- H. Koc, S. Tosun, O. Ozturk, and M. Kandemir, Task Recomputation in Memory Constrained Embedded Multi-CPU Systems, In Proc. IEEE Computer Society Annual Symposium on VLSI 2006 (ISVLSI 2006), Karlsruhe, Germany, March, 2006.

12- O. Ozturk,  M. Kandemir, and S. Tosun, An ILP Based Approach to Address Code Generation for Digital Signal Processors, In Proc. The 16th ACM Great Lakes Symposium on VLSI (GLSVLSI'06), 37-42 pp., Philadelphia, PA, May, 2006.

13- S. Tosun, M. Kandemir, and H. Koc, Using Task Recomputation During Application Mapping in Parallel Embedded Architectures, The International Conference on Computer Design,CDES'06, June 26-29,2006, Las Vegas, USA.

14- S. Kahramanli and S. Tosun, A Novel Essential Prime Implicant Identification Method for Exact Direct Cover Logic Minimization, The International Conference on Computer Design,CDES'06, June 26-29,2006, Las Vegas, USA.

15- O. Ozturk, M. Kandemir, M. J. Irwin, and S. Tosun, Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors, The Twelfth International Conference on Parallel and Distributed Systems, ICPADS'06, 383-390 pp., Minneapolis, MN, July, 2006.

16- Suleyman Tosun, Nazanin Mansouri, Mahmut Kandemir, and Ozcan Ozturk, An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors, ISCIS 2006 Proceedings (LNCS volume 4263). 

17- O.Ozturk, M.Kandemir, M.J.Irwin, and S. Tosun, On-Chip Memory Management for Embedded MpSoC Architectures Based on Data Compression, IEEE International SOC Conference (SOCC 2005), Washington, D.C., September 2005.

18- S. Tosun, N. Mansouri, M. Kandemir, and O. Ozturk, Constraint-Based Code Mapping for Heterogeneous Chip Multiprocessors, IEEE International SOC Conference (SOCC 2005), Washington, D.C., September 2005.

19- G. Chen, M. Kandemir, S. Tosun, and U. Sezer, Reliability-Conscious Process Scheduling under Performance Constraints in FPGA-Based Embedded Systems, The 12th Reconfigurable Architectures Workshop (RAW 2005), April 4-5, Denver, Colorado, USA.

20- S. Tosun, N. Mansouri, E. Arvas, M. Kandemir, Y. Xie, and W-L. Hung, Reliability-Centric Hardware/Software Co-design, 6th International Symposium on Quality Electronic Design (ISQED'05), March 21-23 2005, San Jose, CA, USA.

21- S. Tosun, O. Ozturk, N. Mansouri, E. Arvas, M. Kandemir, Y. Xie, and W-L. Hung, An ILP Formulation for Reliability-Oriented High-Level Synthesis, 6th International Symposium on Quality Electronic Design (ISQED'05), March 21-23 2005, San Jose, CA, USA.

22- S. Tosun, N. Mansouri, E. Arvas, M. Kandemir, and Y. Xie, Reliability-Centric High-Level Synthesis, Design, Automation, and Test in Europe 2005 (DATE'05), 7-11 March 2005, Messe Munich, Germany.

23- S. Tosun, H. Koc and N. Mansouri, Deriving Intermediary RTLs for Verification of Pipelined Synthesized Designs, Proceedings of 2003 International Conference on VLSI (VLSI'03), Las Vegas, Nevada, USA, June 2003.