- Assist. Prof. Dr. Murat Aydos, maydos at hacettepe dot edu dot tr
- Assist. Prof. Dr. Ufuk Çelikcan, ufuk dot celikcan at gmail dot com
- Res. Asst. Handan Gürsoy, handangrsy at gmail dot com (Lab)
- Res. Asst. Burcu Yalçıner, burcuyalciner at cs dot hacettepe dot edu dot tr (Lab)
- Res. Asst. Öznur Esra Par, par at hacettepe dot edu dot tr (Lab) Res. Asst. Hüseyin Temuçin, htemucin at cs dot hacettepe dot edu dot tr (Verilog)

- Some example solution videos on K-Map:
- https://youtu.be/PA-1y2yeRYM

- https://youtu.be/xJxzcvwztjE

- Verilog Project Due
date is to be announced.
**In this project, you are not supposed to provide a testbench but in order to verify your design you need to write a testbench.)** - Verilog homework (The link will be active when an assignment is made)
- BBM233 Logic Design Lab Sheets
- Lecture Notes - Chapter 1
- Lecture Notes - Chapter 2
- Lecture Notes - Chapter 3
- Lecture Notes - Chapter 4
- Lecture Notes - Chapter 5
- Lecture Notes - Chapter 6
- Lecture Notes - Chapter 7
- Lecture Notes - Chapter 8
- Lecture notes were prepared by Dr. Erkay Savaş.

- Verilog - Section 1
- Verilog - Section 2
- Verilog - Section 3
- Verilog - Xilinx ISE v14.6
- Lecture notes (1,2,3) were prepared by Res. Asst. Hüseyin Temuçin.

- Explain how a logic circuit works (Analysis)
- Design a circuit that behaves in a predefined fashion (Synthesis)
- Express a logic circuit in Verilog HDL

- Course Hours: Wednesday 09:30 - 12:30, (Dept. of Computer Engineering, Section 1: D03 -- Section 2: D04 -- Section 3: D09 )
- Midterm : 22.11.2017

- Midterm %35
- Final %50
- Verilog Homework %5
- Verilog Project %10

- Digital Design: With an Introduction to the Verilog HDL, M. Morris Mano, Prentice-Hall, Inc., 5th edition.

- Fundamentals of Digital Systems Design, V.T. Rhyne, Prentice-Hall, Inc.
- Digital Fundamentals, Thomas L. Floyed, A. Bell & Howell Company.
- Principles of Digital Design, Daniel D. Gajski, Prentice-Hall, Inc.

Department of Computer Engineering

e-mail: maydos at hacettepe dot edu dot tr